The present invention relates to manufacturing technologies of semiconductor devices and in particular to a technology effectively applicable to a semiconductor device formed by planarly arranging multiple semiconductor chips.
For example, Japanese Unexamined Patent Publication No. 2004-356382 (Patent Document 1) discloses the structure of a semiconductor integrated circuit device (semiconductor device) formed by planarly arranging multiple semiconductor chips. The structure disclosed in Patent Document 1 is such that: in wire-bonded semiconductor chips A and B, the thickness of the semiconductor chip A on the ball bond side is made larger than the thickness of the semiconductor chip B on the stitch bond side.
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2004-356382